Thin film solar cell manufacturers create expensive products consisting of a number of stacked thin layers. FIG. 1 shows an example of a solar cell in the form of a cross section of the structure of a thin film Cu(In,Ga)(S,Se)2 (referred to as CIGS in the following) solar cell 1. The individual layers of the structure are deposited in sequence on a glass substrate 11. A molybdenum conducting layer 12 provides electrical contact to the backside of the structure. On top of the molybdenum is a light absorbing p-type semiconductor layer 13, which may be selected from CIGS. On top of this is a semiconductor buffer layer 14, which may be selected from CdS, and on top of this are the transparent window layers 15 and 16, comprising firstly an un-intentionally doped ZnO layer 15, and an intentionally doped zinc oxide layer 16.
All layers are important and precise control of the deposition conditions is needed to obtain the required properties from the layers to make an efficient solar device. One problem is achieving the desired control over large areas, which for solar cell applications typically may be of the order of one or more square metres.
Manufacturers would like to verify that the semiconductor layers have been deposited correctly before proceeding to complete the rest of the stack, and thus finishing the solar cell device. They could increase yield and reduce waste in their manufacturing process if they could determine whether the opto-electronic properties of the semiconductors deposited were suitable, over all areas. Typical problems in large-scale manufacturing are inhomogeneous depositions and or inhomogeneous heating during annealing.
A typical solar cell production process is shown in FIGS. 2a through 2f. In a first step (a), a molybdenum conducting layer 22 serving as a back electrode is deposited on a glass substrate 21 (FIG. 2a). A subsequent P1 scribe in step (b) removes the Mo layer 22 in a defined area (FIG. 2b). In a third step (c), the light-absorbing Cu(In,Ga)(S,Se)2 p-type semiconductor layer 23 is deposited (FIG. 2c). Thereafter, buffer layers such as cadmium sulphide layer 24 are deposited in step (d), as shown in FIG. 2d, Subsequently, in step (e) the transparent window layer 25 comprising un-intentionally doped zinc oxide is deposited on top of the CdS buffer layer 24 (FIG. 2e). A final P2 scribe in step (f) removes all deposited layers 23 through 25 until the Mo conducting layer 22 is exposed in a defined area 26 (FIG. 2f). Not shown in FIG. 2, a final intentionally doped zinc oxide layer may be added to the stack connecting two individual cells.
To know whether the semiconductor layer(s) will perform correctly in the solar cell device manufacturers currently use indirect measurements to ascertain that the material has particular properties which can be linked to particular performance characteristics. Two indirect measurements of absorber layer semiconductor material quality are known: Raman spectroscopy and life time photoluminescence. It is found that the width of a characteristic Raman response peak of Cu(In,Ga)(S,Se2) correlates with the final maximum voltage that the device will be able to produce. Also, the life time of luminescence of the absorber layer after excitation with a laser correlates to final device performance. Furthermore, the conductivity of the absorber layer may be measured by mechanically pressing against the absorber layer and measuring its conductivity.
At the moment there is no direct inline method for determining how much electrical current the device will produce, what part of the solar spectrum the device will absorb (band gap of device), and what voltage the finished cell will have. Currently, to determine these properties the semiconductor layers must be physically electrically contacted both on the front and back sides. The p-type semiconductor backside is normally deposited on top of a conducting substrate or conducting layer providing a contact at the back. However, the semiconductor front side must also be contacted to allow for testing.
One way to contact the semiconductor front side is to use a solution which is electrically conducting, which itself can be “contacted” by an external electrode, such as platinum. The solution provides a transparent electrical contact which investigative light can be passed through to interrogate the semiconductor. This general technique is known as “photoelectrochemistry” and is somewhat known in the literature (Dale P J et al., 2007 ECS transactions 6; and Duffy N W et al., 2002 J. Electroanal. Chem. 532 207-14). Once the semiconductor is electrically contacted, light can be shone on to it and the opto-electrical properties of the layer can be established. The key advantage is that this solution provides a front side contact which is extremely easy to remove, e.g. by just washing it away, or if the contacting solution is chosen correctly, could form part of the cell making process.
However, the photoelectrochemical techniques described above are limited to the laboratory scale (1×1 cm2 for example) but not on large areas such as metre squared, as actually used in industrial production processes.